The present invention relates to frequency dividers, and more particularly, to frequency dividers capable of division by a plurality of divisors.
Multi-divide frequency dividers are useful in many applications. One such use is in a .DELTA..SIGMA. controlled factional-N phase-locked loop (PLL) modulator. This type of modulator is a cost and space efficient way of implementing continuous phase modulation (CPM). CPM is used to achieve spectrum efficient digital communication, such as in the GSM/DCS system. Although this modulation technique is particularly suitable for mobile stations in cellular communications systems, its application is not limited to them.
A prior art implementation of a continuous phase modulator is depicted in FIG. 1. The information to be transmitted 100 is supplied to a digital signal processor unit 101 that generates therefrom the in-phase (I) and quadrature (Q) components. These are supplied to respective digital-to-analog (D/A) converters 103a, 103b. The outputs of the D/A converters 103a, 103b are in turn supplied to respective low-pass filters 105a, 105b. The outputs from each of the low-pass filters 105a, 105b are supplied to first inputs of respective multipliers 107a, 107b. A first carrier signal 109a is supplied to a second input of the multiplier 107a in the in-phase path. A second carrier signal 109b, that is 90.degree. out of phase with respect to the first carrier signal 109a, is supplied to a second input of the multiplier 107b in the out-of-phase path. The outputs of the multipliers 107a, 107b are then summed in an adder 111 to form the modulated signal 113 to be amplified and transmitted.
Recently, an alternative implementation of a continuous phase modulator was proposed by Riley and Copeland, "A simplified continuous phase modulator technique", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing," vol. 41, pp. 321-326, May 1994. In this alternative implementation, a .DELTA..SIGMA. modulator is employed to control the division factor of a fractional-N Phase-Locked Loop (PLL). Similar approaches are also described in T. A. Riley, M. A. Copeland and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis", IEEE Transactions on Solid-State Circuits, vol. 28, pp. 553-559, May 1993; B. Miller and B. Conley, "A multiple modulator fractional divider", The 44th Annual Symposium on Frequency Control, pp. 559-568, May 1990; B. Miller and B. Conley, "A multiple modulator fractional divider", IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991. W. H. Alexander and D. C. Rabe, Multiaccumulator Sigma-Delta fractional-N Synthesis. Reference is also made to U.S. Pat. No. 5,055,802, issued on Oct. 8, 1991 to W. H. Alexander and D. C. Rabe, entitled Multiaccumulator Sigma-Delta fractional-N Synthesis; and to U.S. Pat. No. 4,965,531, issued on Oct. 23, 1993 to T. Riley, entitled Frequency Synthesizer. .DELTA..SIGMA. controlled fractional-N PLL modulation is a cost and space efficient implementation that has many benefits. For example, it guarantees continuous phase. Furthermore, the modulation, as well as channel selection, can be controlled in a purely direct and digital manner. By using a multi-divide frequency divider (i.e., a frequency divider that is capable of dividing by a plurality of divisors) in the PLL, a .DELTA..SIGMA. controlled fractional-N PLL modulator could easily be used for a multi-band application.
A block diagram of a prior art .DELTA..SIGMA. controlled fractional-N PLL modulator is depicted in FIG. 2. A reference signal 201 is fed to a phase detector 202 together with the phase of the output of a frequency divider 206. The reference signal 201 is preferably a sinusoidal signal having a frequency denoted by f.sub.ref. The output of the phase detector 202 is a pulse that is related to the phase difference between the reference signal 201 and the output of the frequency divider 206. The output of the phase detector 202 is fed to a charge pump 207 and then filtered by a loop filter 208. The output of the loop filter 208 is then applied to a voltage controlled oscillator (VCO) 209. The output signal of the VCO 209 is supplied to the input of the frequency divider 206. As a result of this feedback arrangement, the output frequency of the VCO 205 is driven to equal the frequency of the reference signal 201 times the division factor of the frequency divider 206. Hence, the frequency of the VCO 209 can be controlled by controlling the division factor of the frequency divider 206. In a .DELTA..SIGMA. controlled fractional-N PLL modulator, the division factors are generated by a .DELTA..SIGMA. modulator 210, whose input receives a modulating signal 211.
The frequency divider 206 in the PLL has to fulfill three important requirements in order to achieve the desired modulation. First, it must be able to change the division factor once every reference frequency cycle. Second, it must introduce exactly equal delay for all division factors, in order to avoid extra nonlinearities in the loop. Third, it must be able to accomplish a wide range of consecutive division factors in order to make the .DELTA..SIGMA. controlled fractional-N PLL modulator work at a wide range of radio frequencies, and thereby accomplish the multi-band functionality.